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PHYSICAL DESIGN/SYNTHESIS
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With the tSilicon state-of-the-art design methodology, our highly skilled engineering teams, and our proven track record of successful tapeouts, tSilicon is the only place to come for Physical Design support. We have taped out devices down to 28nm, closed timing on devices with clocks rate >>1.5Ghz, worked with chips having > 100 million gates and achieved utilization metrics which exceeded our Customers expectations.
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Design Services:
•Top level Design Analysis and planning.
•Power distribution and clock panning
• Floorplanning
• DFT Insertion
• Design for Manufacturability
• Design for Power
• Place & Route
• Clock distribution (CTS, HTree etc.) and analysis
• Scan restitching
• Synthesis
• Timing closure - MCMM
• AOCV/Hold Margin
• Physical verification (DRC/LVS)
• Tapeout process
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Areas of Expertise:
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•Top level Design Analysis and planning.
•High performance chips: > 1.5GHz and > 400sq.mm in 28nm, 32nm SOI & 40nm
•Optimization of SOCs for power & performance – Graphics Processors, Networking ASICs, Mobile ASICs, Storage, DSP & Video SOCs & Custom Designs Low Power Design [Multiple Power Domain/ Power Islanding]
•Design for Cost [Die Reduction vs Performance]
•Timing Closure – SSTA, MCMM, SI/AOCV/ Crosstalk
•High Routability & Utilization
•Low Skew Clock distribution network
•DFM & MFY
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Primary Tools:
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•Magma (Blast)
•Synopsys (Jupiter, Astro, StarRC-XT, Formality, ICC, PT-SI)
•Cadence (Celtic, Encounter, Verplex, VoltageStorm, Virtuoso
•Mentor (Calibre)
•Apache (Redhawk)
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Synthesis/Timing/Analysis:
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•Chip/block level synthesis
•Constraint generation and debug
•Static timing analysis and repair
•SI/Timing closure
•Timing paths
•Multi-clock domain
•Hierarchical/chip level synthesize
•Crosstalk/noise analysis
•EM/IRDrop analysis
•RC extraction
•Power/clock analysis
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Tools:
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•Design Compiler, Physical Compiler, IC Compiler, Blast-create, BlastRTL, Primetime, PT-SI, Magma*, Hspice, Celtic, Scripting languages such as TCL, Python, Perl and UNIX shell
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